si3909d characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and sw itching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the ty pical electrical characteristics of the p-channel ve rtical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the puls ed 0-v to 5-v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance netw o rk is used to model the gate charge characteristics w h ile avoiding convergence difficulties of the sw itched c gd model. all model parameter values are optimized to provide a best fit to the m easured electrical data and are not intended as an exact phy sical interpretation of the device. subcircuit model schematic this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. product specification 1 of 2 4008-318-123 sales@twtysemi.com http://www.twtysemi.com
specificat ions (t j = 2 5 c unless ot herwise not e d) pa ra me te r s y m b o l te s t c o n d i t i o n simulated data measu red data unit static gate threshold voltage v gs(t h ) v ds = v gs , i d = ? 250 a 1 . 1 v on-state drain current a i d ( on) v ds = ? 5 v, v gs = ? 4.5 v 1 4 a v gs = ? 4.5 v, i d = ? 1.8 a 0 . 1 8 0 . 1 6 v gs = ? 3.6 v, i d = ? 1.6 a 0 . 1 9 0 . 1 9 drain-source on-state resistance a r d s (on) v gs = ? 2.5 v, i d = ? 1 a 0 . 2 5 0 . 2 8 ? forw ard transconductance a g fs v ds = ? 10 v, i d = ? 1.8 a 3 . 6 3 . 6 s diode forw ard voltage a v sd i s = ? 1.05 a, v gs = 0 v ? 0.78 ? 0.83 v dy namic b total gate charge q g 2 . 5 2 . 7 gate-source charge q gs 0 . 4 0 0 . 4 0 gate-drain charge q gd v ds = ? 10 v, v gs = ? 4.5 v, i d = ? 1.8 a 0 . 6 0 0 . 6 0 nc turn-on delay time t d(on) 1 0 1 1 ris e time t r 8 3 4 turn-of f delay time t d(off) 5 2 1 9 fall time t f v dd = ? 10 v, r l = 10 ? i d ? ? 1 a, v gen = ? 4.5 v, r g = 6 ? 7 2 4 source-drain rev e rse recov e ry time t rr i f = ? 1.05 a, di/dt = 100 a/ s 2 0 2 0 ns not e s a. pulse test; pulse w i dth 300 s, duty cy cle 2%. b. guaranteed by design, not s ubject to production testing. si3909d product specification 2 of 2 4008-318-123 sales@twtysemi.com http://www.twtysemi.com
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